Hello,
I would like to get 4DSP StellarIP reference design kc705_fmc151 to work in Vivado 2014.3 and I wonder if I could get some advice in this forum.
So far I've imported the VHDL source, except for Xilinx IP modules, which I added in Vivado by hand, using original settings from reference design . The reasoning was that new IP comes with proper internal constraints for Vivado. I've imported pin-out constraints. Clocking constraints were created from scratch, including creating several asynchronous derived clock groups.
I was able to generate a bit file and run it through tests with FMC15xAPP. Vivado still complains that there isn't a dedicated clocking route from IDELAY2 to BUFG as I have mentioned previously here -
http://www.4dsp.com/forum/index.php/topic,2862.0.html. That was confirmed by Xilinx for me.
The design mostly works, bug the ADC ramp pattern test in FMC15xAPP reports 0.25 to 0.5 % error rate. I saved recorded ramp pattern and there is an occasional single bit error, typically in the same bit rank. Is it possible that align_machine does not produce optimum results in Vivado? Or could this error come from clock domain crossing?
I wonder if Vivado timing implementation is too optimistic and one needs to specify setup and hold constraints for the I/O. Is there any documentation on FMC150/151 I/O timing parameters?
Thanks in advance for any advice ion this matter.