Thank you for your responsibility but look, There is a major problem.
in the example of changing fifo from 64 to 128, we are not really engaged with changing the interfaces required for the XilinxIPcore to be compliant with stellarIP environment, specifically, we dont really change the following files:
fifo64k.vhd
fifo64k_regs.vhd
fifo64k_stellar_cmd.vhd
unless some renaming. custom designs does not neccessarily have the same IO, timing, ...
So, In order to realize what is really happening inside the system, designer need to insert chipscope into the design to watch the way signals are exercised in the system(simuilation does not provide practical help)
The chipscope is really cumbersome and frustrating. Do you have any example, create a stellarIP core from NEW hdl codes, creating interfaces and inserting into the StellarIP environment? I believe such a high tech boards, deserve much better documentation.