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Systematic Design Methodology with FMC ADC

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karen:

Thank you for your responsibility but look, There is a major problem.


in the example of changing fifo from 64 to 128, we are not really engaged with changing the interfaces required for the XilinxIPcore to be compliant with stellarIP environment, specifically, we dont really change the following files:
fifo64k.vhd
fifo64k_regs.vhd
fifo64k_stellar_cmd.vhd
unless some renaming. custom designs does not neccessarily have the same IO, timing, ...


So, In order to realize what is really happening inside the system, designer need to insert chipscope into the design to watch the way signals are exercised in the system(simuilation does not provide practical help)


The chipscope is really cumbersome and frustrating. Do you have any example, create a stellarIP core from NEW hdl codes, creating interfaces and inserting into the StellarIP environment? I believe such a high tech boards, deserve much better documentation.

arnaudNL:
Dear Karen,


I appreciate the fact you are disappointed about our reference and documentation. The thing I don't understand is whether or not you are blocked, cannot moved forward or is it some feedback you are providing us.


If you are blocked on something, please let me know what this is and then I will provide you with answers to your questions. Otherwise, please let me know so I can lock this topic.


Best Regards.
Arnaud

karen:
Arnaud




1. Should I continue with your simulation scripts and inserting Chipscope into the design to completely understand the interface you are using in the stellarIP, or there is another way to do that?

A possible solution might be creating a completely new "star", creating the StellarIP interface codes from scratch and importing into design ... , Do you have such an example design?





2. My problem is that, I created a wrapper for my HDL codes, based on the fifo example, but the output I'm getting on PC side is all zero. I cannot verify whether my interface (from HDL codes to StellarIP) is the problem or not, What is the solution for that?

arnaudNL:
Dear Karen,


Creating a complete star from scratch is covered by XFFT training material. A star is created from scratch and an AXI interface core is wrapped by the star.


Please let me know if you have any other questions before I close this topic.


Best Regards,
Arnaud

arnaudNL:
Dear Karen,


I see you have edited your posted and added a second question. As far as this question is concerned, have you simulated your design? I don't know about you but our firmware engineers are always simulating their designs. moving to implementation as soon that is working but they are not coding and implementing their design without simulation.


The fact you get data on the PC side means that the transfer between the host interface and the host worked fine, for the rest, simulation/chipscope will tell more. You will need these tool during your development, this is certain.


Thanks,
Arnaud

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