Topic: how to use fmc160 with an external clock sampling at 1.1GHz  (Read 3505 times)

leongnrl September 02, 2014, 04:11 PM

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I want to use my fmc160 to sample data at 1.1GHz using a 1.1 GHz external clock. How do I do it?

I am using the reference design on VC707. The reference design uses a C program to send ethernet commands to the VC707 to configure the fmc160. Eventually I will need to setup the fmc160 configuration inside the fpga without any help from the ethernet port.

Thank you,

Victor
  • « Last Edit: September 02, 2014, 05:22 PM by leongnrl »

arnaudNL September 03, 2014, 04:30 AM (#1)

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Dear Victor,


The reference C application can setup the chipset for either internal and external clock mode, this is decided by the fourth argument passed to FMC160App.exe. The first thing you wanna do is to get FMC160App to operate with your external clock. The design should work the same for external and internal clock, assuming the external clock is 1800MHz (+8dBm). You will also need to look into the clock tree settings to maybe divide your clock differently, etc.


Then you will want to create a list of the required register read/write the software is doing through sipif_writesipregsiter.


Finally you want to replace sip_mac_engine in the firmware with a state machine pushing the value at given addresses the same as the firmware did.


Bottom line, it wont be as simple as writing 1100 in a register to get 1.1Ghz sampling rate, the chip set is rather complex


Best Regards,
Arnaud

leongnrl September 03, 2014, 11:23 AM (#2)

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Thank you arnaudNL,

I understand this won't be a a simple task. Actually I am using the fmc160 as an example to eventually get fmc161 to sample two channels at 1.1GHz. I realize that there is clock div by 2 component SY89312V in the adc external clock path. To me, it seems like my external 1.1GHz clock will be divided to 550MHz when it gets to the ADC. Is there any other way that I can feed my external clock directly into the ADC?

My another option is to use a 140MHz divided clock as a reference to generate 1.1GHz using the ADF4351. I understand that the ADF4351 is programmed through SPI, and the SPI is translated from I2C using a CPLD, which is accessible using the sip_i2c_master module. Do you have register tables for the sip_i2c_master module that lead me to a setup that generate internal 1.1GHz using a 140MHz external reference?

iklink September 05, 2014, 06:10 AM (#3)

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Dear Victor,


The CPLD I2C to SPI bridge is located at I2C address: 01111xy where x = GA0 and y = GA1 (VITA57 Geographical addressing), you might also want to refer to the FMC160 user manual. The fmc160_clocktree.cpp file in the reference app gives an example on how a SPI write is initiated via the I2C to SPI bridge in the CPLD. The registers that are written in this piece of code (reg0 to reg5) map directly to register 0 to 5  of the ADF4351. For the details, please have a look in the datasheet of the ADF4351, figure 23. This figure also shows that, for selecting each one of the registers, bit[2:0] are used.


Best regards,
Ingmar van Klink

arnaudNL September 10, 2014, 04:58 AM (#4)

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Dear Victor,


Was the information sufficient, would you like to receive more information before I close this topic, feel free to open any new topic anytime you need that.


Best Regards,
Arnaud

leongnrl September 10, 2014, 12:38 PM (#5)

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is the address for fmc160 the same as fmc161?

iklink September 11, 2014, 04:13 AM (#6)

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Dear Victor,


Yes, the address for the FMC161 is the same.


Best regards,
Ingmar van Klink

arnaudNL September 12, 2014, 05:59 AM (#7)

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Dear Victor,


Can I go ahead and close this topic? Was the information received sufficient?


Best Regards,
Arnaud

leongnrl September 12, 2014, 11:09 AM (#8)

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yes. Thank you for your help

arnaudNL September 12, 2014, 11:46 AM (#9)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.