Topic: About GBTCLK_M2C_P/N reference clocks of FMC176 boards  (Read 2384 times)

Clive.Boyd August 12, 2014, 03:26 AM

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Hi all,
I am just wondering about the FMC1 pins GBTCLK_M2C_P/N<0> (JESD 204B ref clock) generated by FMC176 board. Is this signal generated by ADC AD9250? I could not find this pin on datasheet of this ADC. Also, how can we configure the frequency of this signal? and how is it related to sampling clock of the ADC?
Thanks,



iklink August 18, 2014, 09:53 AM (#1)

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Dear,


The GBTCLK_M2C is the transceiver reference clock used by the carrier board MGTs. The FMC176 is equipped with the AD9517 PLL which generates the clocks for the ADC/DACs and the GBTCLK (refer to the User Manual, figure 6).  In the standard reference app, this clock is configured to have 1/2 the frequency of the ADC Sample clock. When configuring the transceiver inside your FPGA, you should set this frequency to the same value to make sure the transceiver will lock to the serialized data stream received from the ADC. If you want to change your ADC sample rate you have to make sure that the new reference (GBTCLK_M2C) clock, provided to the MGT is within the frequency range of the receiver PLL.


Best regards,
Ingmar van Klink



arnaudNL August 21, 2014, 06:09 AM (#2)

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Dear Clive,


Was the information received sufficient, can we close the topic?


Best Regards,
Arnaud

arnaudNL August 26, 2014, 05:29 AM (#3)

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Dear Clive,


I will close the topic in 24 hours without news from your side.


Best Regards,
Arnaud

arnaudNL August 27, 2014, 08:40 AM (#4)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.