Dear Arnaud,
thanks for your reply. I was able to run the reference design. Moreover, I was able to see the digitized signal on my computer. So we can conclude the CPLD works. Moreover, I was able to do that without actually needing an external clock. I can assume that the internal reference and internally-generated clock works well as well.
Now, I would like to interface the sip_fmc125 directly from my xilinx ise environment, embedding it in my custom application, moreover, configuring it directly from my FPGA. Everything goes well. I am making progress with my design. However, I am not able to select the internally generated clock using the internal reference.
This is how I try to configure the A/D to select its interally generated clock (using internal reference):
First I configure x0600 by the following value.
addr: x0600, data: 00000000000000000000000000000110
I verify whether this x0600 has really been programmed by reading its value after its write operation. I can conclude that x0600 is well-programmed.
Now, I need to write x1600. This is the only 'special' register I need to write since it uses the I2C protocol to interface with the CPLD. The other registers are actually part of the RTL-blocks running on the FPGA. These do not use the I2C. This is the data I want to prgram:
addr: x1600, data: 00000000000000000000000000011110.
Reading the manual I see that 110 for CLKSRC means 'internal clock, internal reference'. That is the value I want.
Additionally, I chose 11 for SYNCSRC meaning 'No Sync'. I think the A/D does not wait for a trigger doing this. Anyway, I think that the actual value of this SYNCSRC does not matter.
Reading x1600 I see all zeroes. I am clearly doing something wrong. Not sure whether this happens while writing or reading.
I think this has something to do with the I2C interface. Maybe the I2C interface assumes that the cmd_clk has a particular value. Moreover I think that this value should be stored in the PRER-register of the SC18IS602B_CTRL block.
Arnaud, reading the 'FMC125 Star Quad 8-bit 1.25 Gbps ADC Daughter card' pdf documentation, which I consider as a datasheet for the 4DSP VHDL-module sip_fmc125, I should have enough information to interface the board and its VHDL firmware. However, to my opinion there are still too many question marks I needed to fill in myself, e.g. timing diagram of the read and write operations, the value I need to write to the PRER-register... Since I ve been investing a lot of times in this A/D over the last week I was able to figure out everything reading through the VHDL-files itself. However this I2C is still an open issue.
I see two possible outcomes here:
-either we can have a phone call on this issue,
-either you have some kind of stripped-down runnable model of how to write register x1600. Writing this register is not as straightforward as writing the others in my opinion.
Regards,
Thank you,
Tom