Public Access > General Discussion

FMC 164/168

(1/1)

pnumer:
I was told that the ADC chips on these boards could be configured such that they capture data out of phase with respect to each other - is that true and if so how to you configure them?

iklink:
Dear,


This is not the case, the ADCs are all sampling on the same clock. The ADC chips don't have a feature to delay/phase shift the clock internally.
The ADC chips have settings for delaying the QDR/DDR output clocks but this is the digital domain and not the sampling clock.


Best regards,
Ingmar van Klink

arnaudNL:
Dear Sir,


With you permission I will lock this topic, the issue being asserted I believe.


Best Regards,
Arnaud

arnaudNL:
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.

Navigation

[0] Message Index