Topic: FMC 164/168  (Read 2731 times)

pnumer July 03, 2014, 05:51 PM

  • Member
  • *
  • Posts: 10
I was told that the ADC chips on these boards could be configured such that they capture data out of phase with respect to each other - is that true and if so how to you configure them?

iklink July 04, 2014, 06:03 AM (#1)

  • 4DSP Staff (EU)
  • Member
  • *
  • Posts: 153
Dear,


This is not the case, the ADCs are all sampling on the same clock. The ADC chips don't have a feature to delay/phase shift the clock internally.
The ADC chips have settings for delaying the QDR/DDR output clocks but this is the digital domain and not the sampling clock.


Best regards,
Ingmar van Klink

arnaudNL July 07, 2014, 04:21 AM (#2)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
Dear Sir,


With you permission I will lock this topic, the issue being asserted I believe.


Best Regards,
Arnaud

arnaudNL July 09, 2014, 07:45 AM (#3)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.