Hi Luis - This is a custom logic in FPGA on KC705. The address to the CPLD is 7'b0111100. When I want to do a read, I will send a 1'b1 after the address. So the final command will be {address, read_bit} = {7'b0111100, 1'b1} = 8'b01111001 = 8'h79...this is what I do in step #6. I do get an ack from the CPLD for this command.
The address in step #7 is the address of the version register which is 0x03as mentioned in the CPLD register map in Appendix.B of FM160 user manual.
-Venka