Dear Sir,
1) The interrupt star generates a interrupt packet via the command bus towards the host interface, there are several operations available on the command bus, typically read, write, etc.. The host interface is then placing the mailbox value on a BAR register and asserts interrupt.
2) Indeed there is no FIFO for Host to FPGA mailbox but there is a software FIFO in the device driver to queue FPGA to host mailbox.
3) A mailbox is any 32 bit value, you can put anything you want in there. This could be a size to offload, channel information, etc.. interrupt_16 star is an example of an implementation around the mailbox.
Your understanding of the sequence is correct but only 3) requires correction. Calling 4fm_readmailbox causes the API to try reading a value from the mailbox queue in the device driver, there is a sleeping semaphore waiting on a value to placed in the queue, the queue being filled by the device driver as soon an mailbox interrupt is received from the operating system.
I hope that helps,
Arnaud