Topic: ADC/DAC registers of FMC110  (Read 9427 times)

kanzabaig June 05, 2014, 12:53 AM

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Hello,
I am using FMC110 with ml605, configuring the FMC via Ethernet and everything is working fine. Now as a next step, i want to configure ADC/DAC directly via FPGA by setting register values in the verilog programming. Can anoyone please help me by indicating the ADC/DAC registers in reference design or by informing me that in which sub-module these registers are located.

Thanks and Regards

arnaudNL June 05, 2014, 04:20 AM (#1)

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Dear Sir,


Could you let me know which reference design you are using?


Best Regards,
Arnaud

kanzabaig June 05, 2014, 04:37 AM (#2)

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i am using ref design for ml605 board.

arnaudNL June 05, 2014, 06:55 AM (#3)

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Is it the 4DSP or Avnet design?

kanzabaig June 06, 2014, 03:55 AM (#4)

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its a 4DSP design

arnaudNL June 06, 2014, 04:37 AM (#5)

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Dear Sir,


4DSP design have a ROM Init portion using Xilinx core, there you can set other default value. You can check star_lib\sip_fmc110\vhdl\v7\xilinx\ads5400_init_mem


I hope that helps,
Arnaud

kanzabaig June 09, 2014, 12:47 AM (#6)

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Consider the attached document's page 18. A serial register map is mentioned. In my current design these values are set or the register configuration is sent via Ethernet. I want to make this register independent of Ethernet by setting these values internally in VHDL/verilog code.As far as i can understand these register values can be pinned in the module fmc110_ads5400_ctrl.vhd. Please suggest if i can do so.
My understanding of the code is,
out_reg_addr: It is the address index
out_reg_val : Enable input for writing the register
out_reg        : It is the value to be written in the register

arnaudNL June 10, 2014, 05:32 AM (#7)

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Dear Sir,


Documenting the low level aspect of the firmware line by line is not covered by standard technical support so do modifications on the reference.


You can also try to to simulate the design to help understanding.


Lastly, please consider my ROM Init scheme. You can modify the values and use coregen to recompile the netlist. (.coe, .mif .xco).


If you need extra training or help for modifying the reference design, please contact sales@4dsp.com


Best Regards,
Arnaud

arnaudNL June 13, 2014, 08:15 AM (#8)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.