Creating an interface VHDL design for FMC 151

Hi,


I would like to create a VHDL design which stores ADC values in a FIFO. From my understanding, the VHDL design configures the FMC board through an I2C bus. Data output is received to the FPGA as a differential pair. There is also clock and control signals between the FPGA and the FMC board.


I am trying to understand the communication protocol that is implemented here so that I can replicate it in my design. Is there any documentation from 4DSP that describes the hardware interface between the FPGA and the FMC board.


I looked into the reference design of the ML605 reference design for FMC 151. In the reference design, I noticed that sip_fmc_151_0_adc0_out_data(64 bit) and sip_fmc_151_0_adc1_out_data(64 bit) are the ADC values produced by the SIP_FMC151 module. I examined the values of this signal in chipscope but I am not able to interpret these signal. Is it possible to get information on the bit-organization of these signals?


regards,
Paul

Dear Paul.

Do you still need this information?

Best Regards,
Arnaud

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.