Hi,
I am a collaborator working with Paul on this design. I think it might help to provide some context for this problem.
We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.
We modified the reference VHDL, but during synthesis in ISE, we are having difficulty meeting timing. So, there are two issues:
1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?
Thanks!