Noise with FMC151

Hello,


I ran the same test, this time connecting to channel 1 instead of channel 2 and I get much better results. The text files are uploaded. But still, in the analyzer, I still see lots of noise.


Please suggest a solution for this problem.


When I see the adc1.txt files, I see values from -31,000 to 32,000. With a 14 bit ADC, I expect values from 0 to 16383 or from -8192 to 8191. How is it possible to interpret the values


Thank you.


regards,
Paul

The values are 16 bit aligned, so this is normal that you'll see the results up to +/- 32k.

However, the signal looks clipped (i.e. overpowered).    Usually when it's overpowered, you get that type of waveform where the harmonics are completely overpowered. 

Also, how high is the temperature on the ADC board?  I assume there is a fan or some cooling on the ADC board?  It gets really really hot and it could be damaging to the board if there is no cooling.

Can you build the reference application with Visual Studio?   Our firmware/hardware engineers suspect perhaps a timing issue on that particular board (timing adjustment might be needed).   

You can also feed an external signal in but making sure it won't over clip the ADC and see if the result change.  Please only use the reference application when you do this type of data capture.

 If you can tweak the reference application, you can change this:

 2. If they are setup they can tweak the tapiod_clk value in main.cpp. The range is from 0 to 31                case CONSTELLATION_ID_FMC151_ML605:                                printf("Found ML605 hardware\n\n");                                tapiod_clk = 0x00; tapiod_data = 0x00;                                break;
 the range for tapiod_clk is from 0 to 31.   if you can't change it perhaps I can build you binaries that has differnet values (5, 10, 15, 20) to try out.   


Tony

Hello,


Yes. The temperature of the board is a high. We don't have any cooling mechanism and the board do not have any cooling system either. 


It would be great if you could build the binaries after building the reference application so that I can test it. We are already occupied with the design part of the project and we are loosing too much time because of the problems in the board.


If there is a timing issue with this board, I could check everything with a spare ML605 board and see if I have any problem. When I give external signal, how do I make sure that the signal does not get clipped by the ADC?




Our deadline for deliverables are approaching and hence I would like to know if we can get a new board shipped to us. Once we get the new board,  we can ship-out the old board.This will enable us to work atleast with the channel 1 of the ADC.


Paul

I would start the generator with -3 dBm power and slowly go up.  You should not see data near 32k or -32k at that point.

The harmonics that I see from your latest output shows that the signal seems to be clipped.   Also, I assume you look at the generator waveform, right?

On the software - you guys do not build the C code at all?  How do you test your own design?  I can provide the binaries but at some point you will need to build the code.

Anyway, I will send you a few RAR files of various settings shortly of the executable.

On cooling - you must have  fan blowing on the FMC151 card or another air cooled mechanism.  If not, the board could be damage and you can definitely see problems that you're currently experiencing.   You can use a desktop fan for this if you don't have the other types.  Basically it has to be air cooled.

Attached are two RAR files - tap delay 5 and tap delay 10.   Please run it in command prompt in administrator mode and let me know if it works or not.

You will need to run this file on a computer that has the BSP installed (so the appropriate DLLs are in the path).

Also, what revision of ML605 do you have?   we tested them with rev D but there are later boards that can potentially affect timing on the lines - you'll really need to get the code and compile and change the tapiod_clk values in order to adjust the timing differences on the board.

Hello,


I have uploaded the text files for both the tap delays in two posts.


We do not use the software provided by 4DSP much. We use the software just to make sure that the board is working as expected. We added our own hardware units to get the ADC values and do some processing. Values are also generated by our module to the DAC.


We are using a desktop fan for cooling now.  I think we are using an older version of the board as it was purchased at least 1-2 years back.  The FPGA used inside is XC6VLX240T-1FFG1156.

Paul

A Second set of text files is uploaded:


Please note that the DAC is connected to ADC0.


regards,
Paul

Paul,

The thing is, in order to rule out the hardware/firmware issue, we need to run with  a predetermined set of known firmware and software.  Namely, our reference software and default firmware.   Your issue looks similar to basically timing related problems on the clock.  In our reference software, you can adjust it here in main.cpp:

case CONSTELLATION_ID_ML605:
    case CONSTELLATION_ID_FMC151_ML605:
        printf("Found ML605 hardware\n\n");
        tapiod_clk = 00; tapiod_data = 0x00;
        break;

Our hardware/firmware engineers feel that if you return the board, it'll still pass the test we run verifying that te hardware is fine.   The issue with the signal is that we see bit flips (i.e. timing of ADC data coming in to the FPGA).     It's important that the boards (ML605) have similar revisions because some of them will have longer or shorter trace lines from the FMC to the FPGA, that will affect timing delays.

Can you compile the reference software with the reference firmware and try out a few values on tapiod_clk?

Tony

Hi,

The second set is out of range for sure (delay of 10) - i don't see the ADC0 for the first set (delay of 5)  only ADC1.

Sorry,


I will attach all of delay 5 again.


regards,
Paul

Hi Paul,

Are you using the loopback cable (DAC to ADC directly with our default firmware) without an external generator?  You'll need to do that for these tests in order to make sense.  The second set (delay 10) looks like there is a squarewave inserted).

Actually, both of these sets look like ADC0 has a squarewave.    Are you sure you're looping it back directly???

Sorry.


I forgot to do a loop-back and I was monitoring how a square wave would look after the ADC conversion.


I am uploading the loop-back files in these post.


Paul