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FMC150 to KC705 rev.C

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iklink:
Hi,


Do you mean ISE 14.7? What kind of ISE license do you have? According to http://www.xilinx.com/publications/matrix/Software_matrix.pdf , the Webpack license doens't support the xc7k325t.


I wouldn't recommend to use the microblaze for real-time processing, unless you are using ADC/DAC sample clocks in order of 1 to 50MHz, it is highly unlikely that the processor will cope with these datarates. Instead you should just use VHDL to implement this.

iklink:
Hi,


We are investigating your StellarIP licensing. Could you send the file:
C:\Program Files (x86)\4dsp\4FM Core Development Kit\Bins\Log\AutoUpdate.log to forum_admin@4dsp.com , please add a line with the link of this forum topic in the mail.


Thanks

kmcnutt:
We have some VHDL code that your website provides that produces its own sine wave from the FMC card and output this sine wave to the DAC. We however are unable to get the ADC to read in an input, how do we do this?
Here is some of the code from out project. Are the cha_p and cha_n std_logic_vectors the ADC_in ports? These aren't connected to anything, as far as we can see looking at this code.
The project name from your website: kc705_fmc150_ILA3.VHD

 --Clock/Data connection to ADC on FMC150 (ADS62P49)
  clk_ab_p         : in    std_logic;
  clk_ab_n         : in    std_logic;
  cha_p            : in    std_logic_vector(6 downto 0);
  cha_n            : in    std_logic_vector(6 downto 0);
  chb_p            : in    std_logic_vector(6 downto 0);
  chb_n            : in    std_logic_vector(6 downto 0);

  --Clock/Data connection to DAC on FMC150 (DAC3283)
  dac_dclk_p       : out   std_logic;
  dac_dclk_n       : out   std_logic;
  dac_data_p       : out   std_logic_vector(7 downto 0);
  dac_data_n       : out   std_logic_vector(7 downto 0);
  dac_frame_p      : out   std_logic;
  dac_frame_n      : out   std_logic;
  txenable         : out   std_logic;

iklink:
Hi,


The reference design is the correct design to use. This is the design that you tried to use initially. The VHDL file you are referring to is not part of this design, did you get it from Avnet?
If you take the .bit file that comes along with the 4DSP BSP and use the Fmc15xAPP.exe you will be able to acquire samples with the ADC. This .bit file generated from the original 156_kc705_fmc150 StellarIP project. If you are not familiar with StellarIP I would like to point you to the 4FM Getting Started Guide document.


Is your StellarIP working? I think we didn't receive the autoupdate.log did we?


Best regards

arnaudNL:
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.

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