Topic: FMC160 CPLD I2C access  (Read 6285 times)

venka April 06, 2014, 09:59 PM

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Hi- I'm trying to access the CPLD on FMC160 over the I2C bus and so far I have not been successful.
My setup is KC705 with FMC160 (connected via FMC700) on HPC connector. Here are the steps I
take on the I2C bus:
1. Start
2. Send 8'hE9 // Puts the I2C mux on KC705 in write mode
3. Send 8'h02 // Mux Command byte to select Channel #1
4. Stop  (I get an ack for both the bytes above)
5. Start
6. Send 8'h79 // set up CPLD for read operation, I get an ack for this
7. Send 8'h03 // send the read address for version register....I DO NOT get an ack for this.
8. Read the next byte // I read all 1's.
Is there a step I am missing? Thanks!
-Venka
  • « Last Edit: April 06, 2014, 10:35 PM by venka »

lmunoz April 07, 2014, 08:12 PM (#1)

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Hi Venka,


Are you doing this in some customized FPGA design? Are you using your own I2C firmware implementation?


The addresses to the CPLD should look like this


01111XX


So maybe your read address should be


73 and not 03


or


Maybe try reading the settings out the I2C MUX or the voltage monitor to confirm it has the right value and your reading function works.

Regards,
Luis

venka April 07, 2014, 09:33 PM (#2)

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Hi Luis - This is a custom logic in FPGA on KC705. The address to the CPLD is 7'b0111100. When I want to do a read, I will send a 1'b1 after the address. So the final command will be {address, read_bit} = {7'b0111100, 1'b1} = 8'b01111001 = 8'h79...this is what I do in step #6. I do get an ack from the CPLD for this command.
The address in step #7 is the address of the version register which is 0x03as mentioned in the CPLD register map in Appendix.B of FM160 user manual.
-Venka
 
 

lmunoz April 08, 2014, 01:11 PM (#3)

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Hi Venka, I can't really help you with custom designs we just provide the reference design which has examples in how this is done, but to read one byte I'm pretty sure you do this:



1. Start (Master to Slave)
2. Send  01111 11 1  [start address + offset + read bit]  (Master to Slave)
3. Acknowledge (Slave to Master)
4. Received Data (Slave to Master)
7. Not Acknowledge ( Master to Slave)
8. Stop ( Master to Slave)


venka April 08, 2014, 01:40 PM (#4)

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Hi Luis - The I2C address for the slave is 01111XX where XX=GA(0..1), on KC705 XX turns out to be 00. Can you please confirm with the designers on the read process (if the I2C uses 10-bit addressing or not)? What if I wanted to read address 0x07? According to your method it would be {address + offset + read bit} =  01111, 111, 1 = 9 bits.
-Venka
 

venka April 08, 2014, 01:57 PM (#5)

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Also I think the FMC160 reference design works only with VC707, if I use a KC705 I really cannot use the reference design.
-Venka
 

lmunoz April 08, 2014, 02:14 PM (#6)

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What I meant is that you do an addition and an append but I will double check and let you know.




(start address + offset ) &  read bit




(b"01111XX" + b"0011")   & '1'





venka April 08, 2014, 10:04 PM (#7)

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Hi Luis - Any updates on this? Can I get a schematic of FM160? If I know what pins of CPLD are hooked up to DAC?ADC interface I can build my own I2C/SPI controller. I have had the board with me for a week without being able to configure the DACs/ADCs. I cannot use your reference design (since I use KC705). I'm stuck with an expensive card that I cannot use. Thanks!
-Venka
 

lmunoz April 09, 2014, 01:36 PM (#8)

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In I2C you cannot send a byte after the read bit is set, therefore I believe the sequence should be as follows:

 
. Start
. Send 8'h78 // set up CPLD for write operation
. Send 8'h03 // send the address for version register
. Stop
. Start
. Send 8'h79 // set up CPLD for read operation
. Read the next byte
. Stop

venka April 09, 2014, 03:02 PM (#9)

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Thanks Luis...I'll give it a shot and let you know.
-Venka
 

venka April 09, 2014, 11:20 PM (#10)

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Hi Luis - The below commands worked for me.
. Start
. Send 8'h78 // set up CPLD for write operation
. Send 8'h03 // send the address for version register
. Start
. Send 8'h79 // set up CPLD for read operation
. Read the next byte
. Stop

Now, if I have to read the registers on the SPI bus (for eg Address 0x7F of the DAC which should read 0x07). I do the following:
1. Write 0xFF to address 0x07 // set [31:24] of the internal control word to 0xFF
2. Write 0x00 to address 0x06 // set [23:16] of the internal control word to 0x00
3. Write 0x04 to address 0x00 //initiate a 16 bit spi cycle to the DAC
Once I do this, where is the 8-bit data read back from the DAC stored? Is it address 0x04 or 0x05?
-Venka
 
 
  • « Last Edit: April 09, 2014, 11:54 PM by venka »

venka April 10, 2014, 02:44 PM (#11)

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I noticed that if I write to registers 0x04 and 0x05, I always read back zeros.
Write to 0x04
Start
Send 8'h78 //set up CPLD for write
Send 8'h04 // set up address
Send 8'h87 // Send Data (with two bits set)
Stop
Read from 0x04
STart
Send 8'h78
Send 8'h04
Start
Send 8'h79
Read next byte // I read all Zeroes
Stop
How fast can the I2C bus operate? My I2C clock is 40 KHz.
-Venka
 
 

arnaudNL June 13, 2014, 07:47 AM (#12)

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Dear Sir,

Do you still need this information?

Best Regards,
Arnaud

venka June 13, 2014, 02:00 PM (#13)

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No. Thanks for following up!

arnaudNL June 16, 2014, 04:18 AM (#14)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.