Hi Daniel,
Although you've set the ADC_mode to 4, the software still tries to complete the calibration which fails, and therefore you won't get any data samples. Please also change in main.cpp:
const int OffsetCalibrationEnabled = 0;
const int GainCalibrationEnabled = 0;
const int PhaseCalibrationEnabled = 0;
this forces the software to skip all calibration steps completely and you should just get the samples directly.
I still consider the IO delay tuning values as the possible root cause because you've also seen variations from board to board. The datasheet from E2V shows a potentially large device-to-device variation in output timing of the LVDS signals. As you've already found the source code to change these values, I would propose to do the following:
- Make sure you run the test on one FMC only
- Take the real samples and check the FFT plots, I expect a high noise floor on Channel C. Please be aware that these type of timing violations can be caused by temperature variations, and there is always a change that it works fine one out of ten times
- Assuming channel C fails, change the input delay setting of Ch C by decreasing it with 4 and run the test again. If the channel still fails, you should try to increase it with 4. If it still fails (I don't expect so), try steps of 6 and 8. A span of 6 to 10 input delay values should be error free, so you can finetune to a value the lays somewhere in the middle.
- In parallel, have a quick look at the other 3 channels, these should remain unaffected. If one of these channels is on the edge, you might notice this as well and have to perform the same steps as per Channel C
The bit_align_machine.vhd is not needed for this.
Running the reference_design (not the calibration) is not very useful because that design uses an individual LVDS clock per channel which is different from the calibration design. However it is an easy way to get confident that the hardware is doing oke (sometimes the FMC connector gets dirty and connects may become instable).
Best regards,
Ingmar