Dear Forum:
Although I have been able to achieve operation of the FMC104 using only channels A and C at 100MSps, I still have several open issue and would I would like to speak with an engineer on the phone if at all possible.
My questions include:
1. Given that the Zedboard only has LPC support, how does one (or is it required) reset the FPGAs after the AD9510 has been configured and the ADC clocks synchronized? I am seeing issues with ADC coherency and while they could be caused by meso-syncronous clock domain crossing FIFO, I am unclear how the ADCs get reset after I configure the ADS9510.
2. I found that channel E DDR bus violates the channel banking rules for the Zynq7020 as implemented on the ZedBoard with CHE_06 in bank34 and not bank35 with the channel E clock and other DDR signals. Was this intentional or simply a byproduct of different hardware designs? From my perspective I am not sure how to support BUFIO and IDELAYE/IDDR elements across banks. Has 4DSP done this? If so how?
3. I dropped channels E and G from my initial design because of the above and also to reduce total logic. Nonetheless, I have only been able to support IDDR INPUT OFFSET constraints for sampling rates up to about 130MSps. I realize this may be more of Xilinx timing closure issue but given, again, that IO cannot adjust the set-up/hold window for the ADC data outputs because I cannot access the serial ports over the FMC-LPC interface, I wonder what rates has 4DSP been able to support using only the power-up ADC settings? Given the Artix fabric, and my use of a 13-tap IDELAYE for the data bits and zero-tap for the corresponding clock signals, my attempts to set INPUT OFFSET constraints for timing at 210Msps (i.e. 750ps/750ps set-up and hold) and properly delay for the clock-forwarded IDDR timing window has not been successful. Again, how fast a sampling rate has 4DSP obtained using Artix fabric?
Any other timing closure guidance would be appreciated as I have limited experience with this fabric and strategies for meeting IDDR input timing.
Thanks,
Craig