Hi,
Does 4DSP provide any reference design for an FMC having a multi-channel ADC, say an FMC 168, where the data from all the ADC channels are brought to a common clk domain from their individual domains. I would be interested to see such a reference code for any carrier board, preferentially ML605, where all the individual channel clock inputs and data are passed through appropriate buffers, IDELAYs, MMCM...etc and the data is available in a single common clock domain.
thanks
erol