Topic: SERDES Training code in fmc30rf_afe7225.cpp  (Read 3155 times)

BlakeM January 25, 2014, 06:45 PM

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Hi, I'm going through the code for the AFE7225 in the demo / reference design (fmc30rf_afe7225.cpp), and I'm not entirely clear on what's happening in the training section. I have added my own comments to the sections and omitted the sleep and error checking parts. Could you confirm that the comments I have are correct, and answer the questions that are part of these comments? Thanks.


-------------------- Begin Code Paste -------------------------



// Sets DLY_RST (bit 0) to 1 (resets IDELAY on all data inputs from ADC, self-clearing)
// Sets CLK_RST (bit 1) to 1 (resets dividers on all CLK inputs from ADC, self-clearing)
rc = sipif_writesipreg(bar_phy, 0x03);



// Sets IO_RST (bit 2) to 1 (resets the ISERDES on all data inputs from ADC, self-clearing)
rc = sipif_writesipreg(bar_phy, 0x04);


// ?? Table 13 in SD111(sip_fmc30rf).pdf shows bit 4 to be reserved, so I'm not sure what this section does
rc = sipif_writesipreg(bar_phy, 0x10); //set


// ??
rc = sipif_writesipreg(bar_phy, 0x00);//unset



// Checks to make sure INP_CLK_STOP, FIFO_2_AWAY, FIFO_1_AWAY, FIFO_COLLISION and FIFO_ERROR are all 0
rc = fmc30rf_afe7225_readreg(bar_spi, 0x140, &dword); // CONFIG59 register



//Start training
// Sets START (bit 3) to 1 (starts phase alignment on all data input from ADC, self clearing)
rc = sipif_writesipreg(bar_phy, 0x08);


// Is this checking to see if the DLY_RST bit is still set?

rc = sipif_readsipreg(bar_phy, &dword);
   if((dword&0x1)==0x1)
      printf("Ready\n");
   else
      printf("Busy\n");


Both of the following sections are commented out. Is this by design? Does this training actually accomplish anything?



// Increment IDELAY
for (int32_t i=0; i<0; i++) {
   //rc = sipif_writesipreg(bar_phy+0x02, 0); Sleep(2);
}
// Decrement IDELAY
for (int32_t i=0; i<0; i++) {
   //rc = sipif_writesipreg(bar_phy+0x04, 0); Sleep(2);
}

arnaudNL January 28, 2014, 05:00 AM (#1)

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Dear Sir,


All these could be answered by looking at the firmware source code also shipped along with the reference design.


Quote



// ?? Table 13 in SD111(sip_fmc30rf).pdf shows bit 4 to be reserved, so I'm not sure what this section does
rc = sipif_writesipreg(bar_phy, 0x10); //set




// ??
rc = sipif_writesipreg(bar_phy, 0x00);//unset




Writing a '1' to bit 4 is generating a pulse on the SYNCIN signal on the DAC interface. Bit 4 is self clearing so the second write is not required.


Quote



// Is this checking to see if the DLY_RST bit is still set?


rc = sipif_readsipreg(bar_phy, &dword);
   if((dword&0x1)==0x1)
      printf("Ready\n");
   else
      printf("Busy\n");




This bit is mirroring the status of a signal in the firmware, "data aligned"


Quote



Both of the following sections are commented out. Is this by design? Does this training actually accomplish anything?






// Increment IDELAY
for (int32_t i=0; i<0; i++) {
   //rc = sipif_writesipreg(bar_phy+0x02, 0); Sleep(2);
}
// Decrement IDELAY
for (int32_t i=0; i<0; i++) {
   //rc = sipif_writesipreg(bar_phy+0x04, 0); Sleep(2);
}




This is test code to alter the training results if required.




I hope that helps,
Arnaud







arnaudNL June 13, 2014, 07:10 AM (#2)

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