FMC126 the sampled data is not synchronized between multiple channels

Hi,


I tried sampling 2 outputs from my board using FMC126
Used external clock of 2.5 GHz (fs=1.25 Gsps).
The data from each channels is good but between 2 channels
the data is not synchronized.
In different runs the delays between 2 channels are different. ( I gave a sine wave through a power splitter to 2 inputs expecting an overlaping sine wave but it didn't do that)


Does it sample adc0 first then sample adc1 and so on?


How can I make it sample all the ADCs together on the same time instant?


We are using KC705 and FMC126 for our application


thanks

May be the FMC126 is sampling simultaneously but the data transfer through the FPGA and ethernet has a random delay.


I am using this bit file which was provided to us
kc705_fmc126.bit
[/size][/color]
[/size]what can we change??[/color]
[/size][/color]
[/size]attached is the image of a 1MHz sine wave(through power splitter) sampled multiple times through the same setup[/color]

Dear Sir,


The reference design is using a data router star. This router star will eat input data not connected to a destination, the data router is a very simple VHDL module..


On the software side you will see that the loop looks like:


1) Configure router, one input connects to the destination
2) Enable ADC channels
3) Arm
4) Send a sw trigger




So the first modification you want to do is to modify the data router star to not eat data, if the router does not do that you can start to hope for synchronous data.


Also, 4DSP will not be able to help you around every single step ( this is completely outside the scope of technical support ) but we can offer you with the actual synchronous firmware/software including the software calibration algorithm operating fine with 2 and 1 channel mode; contact sales@4dsp.com if you are interested by the paid option. I am attaching the user manual for the calibration.


Best Regards,
Arnaud

Hi,


thanks for your reply.


I was trying to explore this more and I ran into some issues.


I tried to build the kc705_fmc126.xise file with Xilinx ISE 14.7 (in Windows


1) I ran into this

MapLib:30 - LOC constraint V26 on phy_rxer_0 is invalid: No such site on
   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.


so I set the Variable, but then I got several other errors like this one


2)

ERROR:Place:1119 - The I/O components "bd_p_0<4>" and "bd_n_0<4>" are the P- and
   N-sides of a  differential I/O pair. The component "bd_p_0<4>" needs to be
   placed in a IOBM site and component "bd_n_0<4>" in the adjacent IOBS site
   within the same I/O tile. The following issue has been detected:


Can you help tackle this


thanks

Hello,


According to the release note in the firmware source code, the ISE version used to compile the firmware is 14.2 so it never been compiling under 14.7.


The design might just not compile under 14.7. You want to install ISE 14.2 in parallel, configure StellarIP to use 14.2 and retry like that.


As these are Xilinx errors, involving Xilinx might help you to convert the design from 14.2 to 14.7


Best Regards,
Arnaud

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.