In fmc12x_adc.cpp, line 107, there is the following code:
// Apply sync (through CPLD)
rc = sipif_readsipreg(bar_cpld, &dword);
if(rc!=SIPIF_ERR_OK)
return rc;
dword &= ~0x10;
rc = sipif_writesipreg(bar_cpld, dword); Sleep(10);
if(rc!=SIPIF_ERR_OK)
return rc;
dword |= 0x10;
rc = sipif_writesipreg(bar_cpld, dword); Sleep(10);
if(rc!=SIPIF_ERR_OK)
return rc;
I believe this doing a read-modify-write to the CPLD (via SPI via I2C). I see that it reads 0x18, then writes 0x08, then writes 0x18. However, from reading the FMC12x User Manual, the CPLD register only selects the SYNC source, but does not actually assert SYNC. Specifically, it reads that SYNCSRC is No Sync, then sets it to Carrier (trough [sic] SYNC_FROM_FPGA_P/N), then sets it back to No Sync.
If my understanding is correct, this appears to be a bug because SYNC is never asserted. Anyhow, I would appreciate clarification on the matter.