Dear Arnaud,
quick feedback. Finally I can use any external clock (even 40 MHz).
Main part of that external reference is clock tree and few registers responsible for R, P, A, and B values. Each of them is set in different register and has some constrains (written in clock tree, AD9517 datasheet). Main part of clock tree device is Phase Frequency Detector. It compares two numbers: fref/R and fclk/N. Those values need to be the same (or in some cases as close as possible). Then PLL is locked and we can use that sampling clock in ADC.
If I have more questions, I will write them in this topic in future.
Thank you,
Piotr