Products > FMC176

ADC timing for GTX on VC707

<< < (2/2)

Clive.Boyd:
I am also working with FMC176 and VC707 and having problem with the relationship between the serial line rate and the ADC sampling rate. Could anyone kindly explain to me that relationship? It is sampling rate of ADC 1/40 of the serial line rates?

Thanks,

iklink:

Dear,


The serial link rate depends on the ADC sample clock frequency and number of lanes and channels. The relation is (refer to the datasheet of the AD9250):
Serial rate = 1/(L/(20*M*Fs))
with:
Fs = Sample frequency
M = Number of converters
L = Number of serial lanes


By default we set the ADC sample rate close to 250MHz and use both ADCs and both Lanes inside the chip. This results in a link rate of 5Gbps.
If you are changing the sample rate you should also make sure that the MGT reference clock is configured properly, this is OUT4 of the AD9517 clock generator (see FMC176_clocktree.cpp of the reference software). You have to configure clock OUT4 to a frequency which you also have to set as the reference clock frequency in the core_gen transceiver wizard. The last step is to configure the link rate of your transceiver according to the formula above.


Best regards,
Ingmar van Klink

arnaudNL:
Dear Sir,


Was the information sufficient? Can I go ahead and close this topic?


Best Regards,
Arnaud

arnaudNL:
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.

Navigation

[0] Message Index

[*] Previous page