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ADC timing for GTX on VC707

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mattgran:
Hi all,


I'm trying to integrate the FMC176 into a design outside of Stellar IP on a VC707 board. I'm trying to implement GTX transceivers (using the 7 series transceivers wizard) and I have a few questions. Under the usual run conditions for the board (from the example design):


-What frequency clock is available at REFCLK0?
-What data rate are the JESD204B lanes running at?
-What pins correspond to the JESD204b lanes for ADC0, lane 0?


From what I can gather, the reference clock should be 125 MHz, the data rate 5 Gbps, and the serial lanes should be at pins D7 and D8 (which is GTX channel X1Y24). Is this correct?

arnaudNL:
Dear Sir,


The reference design is complete. As soon StellarIP generates  you get a whole ISE project which contains RTL, UCF and project settings and yield into a design operating fine. Firmware ID 348


Best Regards,
Arnaud

mattgran:
And it's an excellent example design, but it doesn't quite fit my specifications. To fit these specifications, I am trying to incorporate the board into a new design. Although I have a new design, it is not working. It may not be working because I do not understand  the original design (for instance, I may have misinterpreted a constraint). To see if I understand your design, I am asking questions about it.


I'm not asking without having tried everything I can think of with the files that came with the board. I have been unable to port the example over to my new design, and I'm going through a lengthy and intensive debugging process to attempt to establish where the error is, so I may begin to fix it. Any help you can offer, even if it is just a simple "yes" or "no" to my question, would be greatly appreciated.

arnaudNL:
Dear Matt,


I will get a firmware engineer to review this post, he can probably come up with quick answers.


Best Regards,
Arnaud

Kyu:
Hello Matt,



--- Quote from: mattgran on October 29, 2013, 02:42 PM ----What frequency clock is available at REFCLK0?
-What data rate are the JESD204B lanes running at?
-What pins correspond to the JESD204b lanes for ADC0, lane 0?

From what I can gather, the reference clock should be 125 MHz, the data rate 5 Gbps, and the serial lanes should be at pins D7 and D8 (which is GTX channel X1Y24). Is this correct?

--- End quote ---


Yes, it's correct. If you open the gtx coregen file, you can see that data rate is 5Gbps and reference clock is set to 125MHz. FMC DP[0:3]_M2C are connected ADC[0:3].


Thanks,
Kyu

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