1) FMC125 MHz is the clk_cmd that is synchronized with 4DSP StellarIP interface. It's not dealt with ADC/DAC clocks. The reason why it uses 122.88Mhz is that actual ADC_DCLK and DAC_DCLK are 368.64Mhz which is generated from the multiple of the reference clock input 30.72MHz. Then it goes through the serdes with 368.64Mhz and 122.88Mhz.
2) DAC uses an interpolation by 2.
3) That should be the theoretical SNR. The board is characterized by TI and TI has not finalized the report yet. The report will be available next couple of weeks.
4) I'm sorry that we do not support schematic. Please, contact the sales.
Please, refer the source codes, datasheets and 4DSP documents.
Thanks,
Kyu