This is for rearranging the sample order. AFE7225_STORAGE_FIFO has a 32bit input and a 64bit output. The read out data from the FIFO has the first sample at bit[63:32] and second sample at bit[31:0]. Thus, sample order is rearranged by swapping the samples. At TX side, FIFO has a 64bit input and 64bit output so the swapping is not required. Please refer to the Xilinx FIFO user manual for more details.
Thanks,
Kyu