Topic: FMC204 configuration (verilog)  (Read 7889 times)

tatonko October 10, 2013, 02:48 PM

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I'm currently involved in a project that uses a VC707 development board, a FMC104 and a FMC204. I need both boards to be configured to be working at 200 MSPS by my own hardware using the SPI connection on the FMC boards.
I've managed to make the FMC104 work and right now I'm completely stuck making the FMC204 work.

This is how I'm doing it right now:

I'm sending these values over SPI to the FMC board (in order):

24'h00001E; --> CPLD configuration for internal clock, internal reference, no sync
32'h8400107C; --> PLL normal mode
32'h84001106; --> R divisor = 6
32'h84001300; --> A divisor = 0
32'h84001403; --> B divisor = 3
32'h84001604; --> Prescaler = 8
32'h84001806; --> reset vco calibration
32'h84023201; --> update regs
32'h8401E000; --> VCO divider = 2
32'h8401E102; --> Selection of VCO and VCO divider
32'h84001807; --> initiate VCO calibration
32'h84023201; --> update regs

If I'm doing right, the VCO should generate a frequency of 400 Mhz (reference is 100 Mhz, so Fvco=Fref·((P·B)+A)/R) which after passing the VCO divider will be 200 Mhz (I'm using the DACs at 200MSPS).

In the FPGA I’m sending the data to the FMC204 using double mode (data A on the positive edge and data B on the negative edge). To do that, I have and ODDR module receiving two data streams and a 200 Mhz clock making the conversion. The resulting data stream is connected to several OBUFDS to generate the LVDS signals to the FMC board. I’m also sending those 200 Mhz over the LVDS clock signals to the first DAC.

As I’m not using more than one FMC204 board, I guess the SYNC signal is kind of useless, so I have it stuck to 0’b0.

I’m not sure what should I expect from the CLK_TO_FPGA LVDS signals. They are tagged as outputs, but the data and clock signals are too when they are obviously inputs.

What should I do with this signal, connect it to a 100 Mhz signal (half the frequency of the data signal) or should I expect to receive a clock signal from the FMC board to generate my internal 200 Mhz clock signal?

On the other hand, I’ve seen that by default, the DAC is configured to work in double mode, so it should receive correctly the data I’m sending. Is there anything more that I should check and/or configure (note that all parameter are at their default values)?

To sum up, these are my questions:

I’m configuring correctly the AD9517-3?
Should I make changes in the default configuration of the DAC5682z?
What should I do with the CLK_TO_FPGA LVDS signal?

Hope you can help me, ask me if you need more info!!

Thanks in advance!

arnaudNL October 11, 2013, 04:34 AM (#1)

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Dear Sir,

Our reference design (firmware/software) does configure the clock tree, have you got the design to operate well? If that works, then you can simply figure out the algorithm involved in the software.

The VCXO on board is narrow range and the internal VCO mode is not supported. You can only divide VCXO loop by n and this is what the reference software does.

Best Regards,