Topic: generating 250 msps signals using reference design  (Read 7515 times)

mahturk October 02, 2013, 03:40 AM

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The reference design produces 500 Msps sinus signal. In the dac IC, it is interpolated to 1 Gsps. My aim was to produce 250 Msps signal in the reference design by simply copying the current sample to the next sample. So the the signal which will be sampled at 500 MHz will look like:

previous case: S0 S1 S2 S3 S4 ...   
new case : S0 S0 S2 S2 S4 S4 ....

Normally, this should result in 250 Mhz sampling rate. I hoped to see the same signal in scope but the signal was corrupted. The signal was no more a pure sinus and the amplitude was about 500 mv.

What may be the reason of it? Therotically, i should see the same signal with a lower sampling rate.

Thank you. 

arnaudNL October 08, 2013, 10:27 AM (#1)

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Dear Sir,

The theoretical aspects seems to be sound. Sure thing is that changing the sampling frequency in magnitude of half is going to produce a "stairy" waveform as you have half of the points. Typically it could be interesting to try that with a slowed DAC output.

Also keep in mind the FMC204 is ac coupled and there is a frequency band limitation, the FMC204 user manual indicates this what this range is.

The amplitude is a bit strange, as if your duplication of samples is not done fast enough. Difference in amplitude can be explained by bit errors.

The first thing I would be trying is to simulate the modification and make sure everything is fine in the digital domain before running on hardware.

I hope that helps,