The PCIe enumeration is done by BIOS and not by Windows/Linux. Reloading FPGA from flash during runtime will cause BIOS to loose the way to the peripheral and this is why a reboot is required.
Arnaud,
I understand that re-loading the FPGA during runtime will cause the OS to loose communication with the FPGA via the PCIe bus. I believe that we could re-establish communication by forcing a re-enumeratoin of the bus. If re-enumeration requires a complete re-boot, that would be acceptable because re-boot can be commanded remotely.
What is NOT ACCEPTABLE for our application is requiring a POWER CYCLE in order to re-load the FPGA. We must be able to force a re-load of the FPGA by remote control.
On the PC720, the FPGA load itself from FLASH, I would assume a POR (Power on Reset) preventing the FPGA to load before power rail are stable.
In our system now, I find experimentally that a re-boot (with power remaining on) does NOT cause the FPGA to be loaded from FLASH. A commanded "shutdown" followed by a pressing the power button to restart also does NOT cause the FPGA to be reloaded; this is because standby power continues to be applied, even though the CPU is shut down. Only complete removal of power from the chassis and then re-applying power causes the FPGA to be loaded. After that, the OS still is not able to communicate with the FPGA until a second re-boot is done. The latter is probably because the FPGA has not finished loading when the BIOS attempts to enumerate the PCIe bus.
We need to find a way to fix this in order for the PC720 to be usable in our application. I believe that a satisfactory fix is possible, but it probably requires modification of the CPLD code. We would appreciate any help you can provide with this.
I have asked several questions in this thread which have still not been answered:
- Can you give a precise explanation of what the present CPLD code does?
- Does the CPLD drive the FPGA's PROGRAM_B pin?
- Exactly what happens when the '4fm_reset' utility is executed or the '_4FM_ResetDevice()' function is called? Is this dependent on having appropriate firmware running in the FPGA or is it handled entirely by the CPLD?
- Can we get a copy of the complete schematic of the PC720 board?
- Can we get a copy of the CPLD source code?
Regards,
Larry