Topic: receive and transmit data continousely  (Read 3783 times)

rvincentzio September 19, 2013, 03:07 PM

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Is there support in the reference firmware and software for repeatedly uploading contiguous blocks of data from the receiver and ADC? I want to create a sw application that uploads blocks of data from ADC to two files alternatively so that I can process one file while the other is written. And something in the same idea for the transmitter.

The reference software transmits a snapshot of data by the functions fmc30rf_ctrl_prepare_wfm_load and sipif_writedata, and uploads the receive data by sipif_readdata; there are other functions to trigger and prepare. I am not sure if and how I can use those functions to handle contiguous blocks of data from the ADC. I hope the reference FPGA firmware can do that.


Vincent

arnaudNL September 20, 2013, 05:12 AM (#1)

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Dear Vincent,


Without number it is hard to formulate an answer. There is a problem of reliability and bandwidth. Anything above a couple of MB/s will not be reliable using ETHAPI. The communication layer is using low level packet manipulation without any packet recovery algorithm and things like length of the cable will already affect your reliability. That's it the ETHAPI was not designed to reliably offload large amount of data. Same goes on the firmware side.


Generally our customers are using Ethernet for evaluating our hardware and then move to PCIe or sFPDP in order to transfer large amount of data. an Ethernet TOE could be implemented in the firmware and then you could maybe go up to 30-50MB/s. The software would then use TCP/IP. a TOE core on firmware can cost up to 70k$ so in this respect PCIe is a cheaper alternative for better results.


This is far beyond the scope of technical support as we are talking about heavy modifications on the reference design. I think you should put number on the paper, how much TX and RX bandwidth you need and then decide what is the best approach. 4DSP can assist you on these steps if an engineering/integration support contract is in place, you can discuss that with sales@4dsp.om


I hope that helps,
Arnaud

rvincentzio September 23, 2013, 12:55 AM (#2)

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My application is quite low bandwidth, the signal is under 1.5 MHz so the sampling rate needs to be about 3 MHz. I want to set the OUT1 of AFE7225 to 12.288 MHz, divide by 80 (instead of 4). The AFE7225 ADC clock is divided this by 2 (unchanged), to 6.144 MHz. I will use the AFE7225 ADC with LPF and decimation by 2, so the offload sample rate should be 3.072 Msamples/s, I and Q. So is possible to transfer this on the Ethernet connection? For the time being I am not concerned with the transmitter and the DAC.

arnaudNL September 24, 2013, 09:14 AM (#3)

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Dear Vincent,


So I assume you have 3m samples per second, one sample is 2 bytes, and you have I/Q so you would need a 3*2*2 => 12MB/s (Mega bytes per seconds).


This might fit or not. Only tests will tell. It will also be system dependent, the complete scheme relies on the host CPU parsing packets and on Windows, because the scheduling, you will not be able to predict a realistic time (not real time).


We did not characterize the Ethernet link because once again it was not designed to stream data back and forth but simply to offload small snapshots. Just try but this sounds too much data for the link.


Best Regards,
Arnaud

rvincentzio September 25, 2013, 03:01 PM (#4)

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Hi Arnaud


Thanks for your answer. To read data from the ADC do I need to apply repetitively the sipif_readdata, or I also need to apply the fmc30rf_ctrl_sw_trigger every time before the sipif_readdata? Where is the documentation of the FPGA reference firmware section that deals with the ADC and DAC? I wanted to see whether there is a way synchronize the readings from the ADC.


Regards,
Vincent

arnaudNL September 26, 2013, 03:59 AM (#5)

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Hello Vincent,


The would be the star documentation for the FMC30RF star (SD111). This doucment is part of the firmware documentation, inside and the firmware package.


Besides this you have the source code and the simulation to help out with the low level internals.


Best Regards,
Arnaud