Hi Erik.
Thanks for your reply.
First, I'll try to explain you better what we are trying to do for you to understand better my question. Off course it's important to tell that this is our first FPGA project, so there are lot of basic concepts that we don't already know.
We have a Xilinx ml605 dev board, and now we've plugged a FMC116. In our FPGA, we have a LEON3 soft-core, and a RTEMS application running, that communicates through ethernet with a host PC. In our application we have several routines implemented that we need, and now we need to access to the samples provided by 4DSP FMC116.
To do that (and maybe here is the first mistake), what we are trying to do, is to create an IP-CORE AMBA compliant to be accessible by our RTEMS application. This IP would only be a wrapper connecting I/O signals of the carrier board, to I/O signals of FMC116 board. And inside our IP, this signals would be routed to an instance of the generated Stellar IP vhdl code (off course without the ethernet star, receiving the commands through our application).
This way, we treat the SIP project as a black box, and that's why I used "black box" in the previous topic.
By now, we have just merged the ucf constraints provided by FMC116ml605 reference design with the ucf constraints of our leon3mp project. We have created a dummy IP-CORE AMBA compliant, checked that it works, and then, we have just tried to add the FMC116 signals to the main entity, and pass them to our IP-CORE. We still have not used any of the SIP generated code.
And doing so, is how we get the errors that I send in the previous topic.
After further tests, we've tried to use IBUFGDS for the DCO signal, in order to have a single-ended signal for the FPGA to work, created by the two differential pins of the original DCO signal.
signal dco_se : std_logic_vector ( 3 downto 0);--Single ended DCO signal after IBUFDS
single_ended_dco: for idx in 0 to 3 generate
ibufgds_dco : ibufgds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
O => dco_se(idx),
I => dco_p_0(idx),
IB => dco_n_0(idx)
);
end generate;
But we are still having problems. In fact, after remerging ucf files and adding missing clock constraints, and using ibufgds, the new warnings that we have are :
WARNING:ConstraintSystem:137 - Constraint <NET "DCO_P_0[0]" TNM_NET = "DCO0";>
[leon3mp.ucf(343)]: No appropriate instances for the TNM constraint are
driven by "dco_p_0[0]".
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_DCO0 = PERIOD "DCO0" 500
MHz HIGH 50 %;> [leon3mp.ucf(344)]: Unable to find an active 'TNM' or
'TimeGrp' constraint named 'DCO0'.
We've checked in the vhdl generated by stellar IP if there is any ibufgds used or any other conversion for the DCO signal or for the CTRL_0 signal, but it seems that it just uses them as we tried at the beginning.
So I hope that now you understand better what we try to do, what we are trying now, and of course we all hope that you can help us solving it. Off course, if you think that the design we are trying to implement is wrong, let us know.
Thanks a lot!
Víctor Martín, IEEC