Topic: How to control the FMC116 board and set important parameters?  (Read 17281 times)

Kyu June 19, 2013, 05:07 PM (#15)

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Xun,


1) Our reference design uses a trainning to find the optimal sampling point. If the sampling frequency is changed, then the trainning has to be run again. Our design uses the serdes and idelay with the bit align machine. This design is suitable for the high sampling frequency. If the low sampling frequency is used, the idelay may be not probably working becuase the total delay of idelay is much smaller than the clock period. New design should be implemented for the low freuqncy. Using IDDR can be a good solution.
2) I'm sorry we cannot help you to understand the PLL configuration. Since we use 100MHz for the reference clock and 10 for R divider, the easiest configuration can be to change the R divier 1.
3) REFIN and CLKIN are connected as a differential pair as shown in Fig 9 in the User Manual.


Thanks,
Kyu

Xun Wu June 19, 2013, 09:02 PM (#16)

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 Kyu,
I found that the DCO and FR signal do not match the timing diagram in the LTC2175 data sheet when the sampling frequency is very high. This makes it difficult to align the data into the right form, doesn’t it? Is the “align machine” you mentioned used to solve this problem? Could you tell me more about this and also about the training you mentioned? Or could you recommend some references?
Xun

Kyu June 20, 2013, 12:56 PM (#17)

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Xun,


Our reference design does not use frame signals. When the trainning starts, the adc outputs the test pattern. The bit align matchine detects the test pattern and adjust the idelay to align the data and find the optimal sampling point. Once the trainning is done, all data is aligned so frame signal is not required.


Thanks,
Kyu

Xun Wu June 21, 2013, 11:33 AM (#18)

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 Kyu,
Could you give some hints about how this bit align machine is designed? Is it possible to design it purely with the ISE project navigator? Could you recommend some references?
Thank you
Xun

Kyu June 24, 2013, 05:27 PM (#19)

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Xun,


You should have source codes for serdes and bit align machine in your reference design. Basically it detects the edges of the data and adjust idelay to the optimal sampling point.


Thanks,
Kyu

dipencha February 27, 2014, 08:31 AM (#20)

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Dear Sun wu
I am too the very beginner in this field so I thought to contact you.
I have FMC126 daughter board and the carrier board is DKXC5VMOD-1,virtex 5 FPGA board.
My project is too similar to you.I want to capture some analog signal and convert them into digital data and display them into PC or somewhere else.
How should I begin? and I dont understand one thing you have said in the early comment.
" It worked! I generated a bit file (although with many warnings together), downloaded it into the FPGA and then called the fmc116 application and finally managed to retrieve some reasonable data."
Can you please elaborate "then called the fmc116 application and finally managed to retrieve some reasonable data" ..
Please explain this in more detail.
Thank you
Dipen

arnaudNL June 13, 2014, 07:24 AM (#21)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.