Xun,
1) Our reference design uses a trainning to find the optimal sampling point. If the sampling frequency is changed, then the trainning has to be run again. Our design uses the serdes and idelay with the bit align machine. This design is suitable for the high sampling frequency. If the low sampling frequency is used, the idelay may be not probably working becuase the total delay of idelay is much smaller than the clock period. New design should be implemented for the low freuqncy. Using IDDR can be a good solution.
2) I'm sorry we cannot help you to understand the PLL configuration. Since we use 100MHz for the reference clock and 10 for R divider, the easiest configuration can be to change the R divier 1.
3) REFIN and CLKIN are connected as a differential pair as shown in Fig 9 in the User Manual.
Thanks,
Kyu