Hello Kevin,
The ADC is continuously acquiring data, the data buffering in the FPGA should be rewritten. I think you will need to simulate/understand the reference design and you will then have a better insight on how to modify the reference design in consequence.
This request is really outside the scope of technical support, you can decide to adapt our reference design (which is provided as source code, free of charge) or to contract us to take care of your integration issues, your decision.
I will give you a few pointers but I cannot do more:
1) What is the bandwidth of the stellarIP data bus connecting A/D and D/A, would this bus be sufficient in term of bandwidth?
2) Do you need external memory for your processing where the reference design only use a 64kB FIFO?
3) Is the fabric running fast enough for you to stream/process all this data?
4) What actual sampling frequency you target as this dictates the data flow?
5) In the reference design , samples are extended to 16 bit, maybe this is not sufficient for your application?
I hope that helps,
Arnaud