Arnaud,
I followed the steps in the 4FM Getting Started and created a new kc705_fmc30rf. bit. Given the following warnings, please let me know if I should download this design to the KC705.
In ISE 14.4 I opened the Plan Ahead program, then "Open Project" for C:\Program Files\4dsp\Common\Firmware\Extracted\227_kc705_fmc30rf\output\kc705_fmc30rf\kc705_fmc30rf.xise. Then I run synthesis and implementation and got the following critical warnings.
- [Constraints 18-11] Could not find net '*/SYSCLK_IN' [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:67]
- [Constraints 18-47] TIMESPEC TS_SYSCLK_P_0 is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 50) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:140]
- [Constraints 18-47] TIMESPEC TS_SYSCLK_N_0 is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 52) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:142]
- [Constraints 18-47] TIMESPEC TS_PHY_RXCLK_0 is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 54) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:144]
- [Constraints 18-47] TIMESPEC TS_q0_clk1_refclk_i is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 65) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:155]
- [Constraints 18-11] Could not find net '*/SYSCLK_IN' [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:157]
- [Constraints 18-47] TIMESPEC TS_SYSCLK_IN is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 68) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:158]
- [Constraints 18-47] TIMESPEC TS_gt0_txusrclk_i is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 72) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:162]
- [Constraints 18-47] TIMESPEC TS_gt0_txusrclk2_i is redefined. The earlier version defined at (file = kc705_fmc30rf.ucf, line = 75) will be discarded [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:165]
- [Constraints 18-329] No definition for group 'SYSCLK_IN', timing constraint is ignored [C:/Program Files/4dsp/Common/Firmware/Extracted/227_kc705_fmc30rf/output/kc705_fmc30rf/Src/kc705_fmc30rf.ucf:158]
After generating bitstream:
Analysis completed Wed Mar 13 11:30:16 2013
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Total time: 37 secs
*** Running xdl
with args -secure -ncd2xdl -nopips "kc705_fmc30rf_routed.ncd" "kc705_fmc30rf_routed.xdl"
Release 14.4 - xdl P.49d (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '7k325t.nph' in environment C:\Xilinx\14.4\ISE_DS\ISE\.
"kc705_fmc30rf" is an NCD, version 3.2, device xc7k325t, package ffg900, speed -2
Successfully converted design 'kc705_fmc30rf_routed.ncd' to 'kc705_fmc30rf_routed.xdl'.
*** Running bitgen
with args "kc705_fmc30rf_routed.ncd" "kc705_fmc30rf.bit" "kc705_fmc30rf.pcf" -w -intstyle pa
WARNING:PhysDesignRules:367 - The signal <phy_col_0_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <phy_rxer_0_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <phy_crs_0_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<sip_mac_engine_0/mac_engine_inst/ge_mac_stream_inst/gmii_eth_rx_stream_inst/
afifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gd
m.dm/Mram_RAM1_RAMD_D1_O> is incomplete. The signal does not drive any load
pins in the design.
Regards,
Vincent