Hey Arnaud,
Thanks for the JED file, will test it right away.
I have looked into the triggering of sync pulses for the AD (the phase calibration on the AD itself covers ranges of +-15ps, that is a magnitude smaller than the phase differences I observe during my measurements). Unfortunately, documentation (SD039) says that setting of the sync bit in ADC PHY command reg is not supported on ML605. Can you tell me why this is the case? I've looked into the VHDL code of the extracted design and all connections, as well as the mapping in the corresponding UCF file, seem to be correct. I've tried to apply the sync pulse nevertheless by modifying the Fmc12x software, but still get delays ranging between 1.2ns and 12ns for a 20MHz input signal (modified the code as well to have a single sw trigger for all channels, get similar delays for 2 channel mode and common mode).
Besides, I observed that there are some slight clock differences between the different ADC's, at least the test application says so. Could this be part of the problem? Here is part of its output (I've disabled channel C and D):
ADC A PHY Clock : 156.25 MHz (Fs = 1250.00)
ADC B PHY Clock : 156.23 MHz (Fs = 1249.88)
ADC C PHY Clock : 0.02 MHz (Fs = 0.12)
ADC D PHY Clock : 0.02 MHz (Fs = 0.12)
With best regards,
Philip