Topic: Config ADC FMC108  (Read 8126 times)

CedricDumezViou December 11, 2012, 05:00 AM

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Hello,

In the file FMC10x Board Support Package/Refs/Software/main.cpp l.234 form the SDK, one can read:
 WriteSystemRegister(0x103F, 0x20);   //int ref, normal operation
i.e. , the value 0x20 in written in register address 0x3F of the ADS62P49 ADC.

We applied the same value in our system and we are facing a strange behavior of the ADC when observing weak signals (TF_BAD.pdf: input channel loaded with 50ohms, note the baseline jumps that can reach up to 2dB from spectra to spectra).

TI's documentation (
http://www.ti.com/lit/gpn/ads62p49 p.21-22) is also strange on this particular register:
- p.21, we are told about a <REF> option located on D6
- p.22, the same option is now a 2 bits valuesD5-D6
- The valid values seem to be described only for D5-D6 equal "00" (internal ref) and "11" (external ref (not to be used on the FMC108)). The other cases are not described but it is one of them ("01") that is selected when 0x02 is written in the 8-bit register.


I tried using the RESET default's value "00".  The problem seems to vanish (TF_OK.pdf, same scales and color-maping of TF_BAD.pdf).
Can you confirm that it is the right way to solve this problem?
Is it something already known or met in other applications?

Sincerely Yours,

Cedric

CedricDumezViou December 12, 2012, 09:33 AM (#1)

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Hello,

The value 0x20 written in register address 0x3F of the ADS62P49 ADC is still strange for me.  As well as the TI documentation about this option.

However, suppressing the Automatic Offset Correction option provides us with good data.
I guess I cleared it without paying attention when I manually reset the ADC (writing 0x80 @ 0x00).

Sincerely Yours,

Cedric

arnaudNL December 12, 2012, 09:44 AM (#2)

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Hello Cedric,


The problem here is about differences between the initial datasheet and last revision of the datasheet. If you look at http://html.alldatasheet.com/html-pdf/292730/TI/ADS62P49/645/21/ADS62P49.html you will see what I mean, internal reference should be 01 which is actually writing a 0x20 in there.. And yeah on the new datasheet, this settings sounds like not valid!


We have asserted that with TI and are waiting for an answer, we are waiting more information from TI. If this relates to new silicon revisions, then we will need to either write 0x20 or 0x00 depending the silicon revision.


I will keep you updated and thank you for this valuable feedback!


Best Regards,
Arnaud

CedricDumezViou December 12, 2012, 09:57 AM (#3)

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Hello Arnaud,

Thank you for your answer.
I see what you mean.

Regards,

Cedric

arnaudNL December 12, 2012, 01:32 PM (#4)

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Hello Cedric,


We have got an answer from TI and they say the datasheet is confusing but actually there are two groups:


- 00, 01, and 10 for internal reference
- 11 for external reference


In other words, '00', '01' and '10' are valid for internal reference.


I guess the problem is more about automatic offset compensation then.


I hope that helps.


Best Regards,
Arnaud

CedricDumezViou December 13, 2012, 06:49 AM (#5)

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Hello,

Thanks for the feedback.
I agree about the automatic offset compensation.

Thanks for your help.

Cedric