Hi Arnaud,
I figured out the PLL lock issue, I was mislead by the settings in the ad9517_init_mem.mif file which configure the PLL to use the internal VCO by writing 0x02 to register 0x1E1. Apparently the clock chip is not wired to use the internal VCO and instead it uses an external VCXO. I would like to know what's the range of this external VCXO and the bandwidth of the filter that follows it.
Regards,
Shant