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| Subject / Started by | Replies / Views | Last post  |
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Reference Design Details
Started by arnaudNL |
0 Replies
9724 Views |
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Adding Registers to sip_fmc30rf
Started by kcfarleyswmacb |
1 Replies
7887 Views |
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reference design help
Started by stanstanev |
2 Replies
5798 Views |
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Iserdes reset
Started by stanstanev |
3 Replies
6473 Views |
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Quadrature phase error in RX stream
Started by stanstanev |
4 Replies
6529 Views |
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Support for FMC30RF and KC705
Started by rvincentzio |
3 Replies
7149 Views |
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Simulator in ISE 14.4
Started by rvincentzio |
1 Replies
5569 Views |
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Design and modeling flow
Started by rvincentzio |
14 Replies
15865 Views |
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MOVED: High and variable I/Q imbalance
Started by arnaudNL |
0 Replies
4355 Views |
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working with the reference firmware
Started by rvincentzio |
9 Replies
8330 Views |
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TRF3765 RFOUT connections and logic
Started by rvincentzio |
1 Replies
4765 Views |
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Clock mode 1 does not work
Started by rvincentzio |
1 Replies
4265 Views |
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8 Replies
7198 Views |
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General questions to FMC30RF
Started by m_a01 |
1 Replies
4280 Views |
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5 Replies
5450 Views |
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1 Replies
4038 Views |
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Ethernet and ML605 with FMC30RF
Started by kcfarleyswmacb |
3 Replies
5224 Views |
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TX ERRATIC SINE WAVE OUT
Started by kcfarleyswmacb |
3 Replies
5122 Views |
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trying to use lower ADC and DAC rates
Started by rvincentzio |
4 Replies
5350 Views |
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FMC30RF FIFO SAMPLE SWAP
Started by kcfarleyswmacb |
3 Replies
4894 Views |
|
These forums will be taken offline, effective March 13, 2015.
Ongoing support will be available at support.4dsp.com
Open support tickets on this forum will remain open with full support until May 31, 2015.
All topics will be archived and available until March 31, 2016
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