Polyphase Filterbank
Description
The polyphase filterbank algorithm is a very efficient way to implement a uniformly distributed multi-channel filterbank using a Fast Fourier Transform. The functional diagram below shows a polyphase filterbank with 256 channels, continuously processing digitized samples coming from a 2GHZ Analog-to-Digital converter (AD491).
The polyphase filterbank core is designed for 16 up to 4096 channels. Slower processing rates to better suit various requirements can be implemented. The data resolution ranges from 8-bit up to 24-bit. A floating-point version of the core is available upon request.
This core can be used for the following family devices:
- Xilinx Virtex II Pro, Virtex-4, Virtex-5, Virtex-6, Spartan3, Spartan-6
- Altera Stratix, Stratix II, Stratix IV, Cyclone II, Cyclone IV
StellarIP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation. A fully functional VHDL test bench and Matlab functions are delivered along the polyphase filterbank core for simulation purposes and specific performance characterization.
Documentation
