IEEE-754 Floating Point FFT/IFFT IP core
For fixed point FFT please visit the fixed point FFT page
4DSP’s Floating Point FFT core is the most flexible IEEE-754 compliant FFT core available in the FPGA world. Designed for high performance programmable devices from Xilinx and Altera, this core performs Fast Fourier Transforms ranging from 256 points to 1M points and is ideal for high precision spectral analysis, radar and video processing applications. Download our bit-true model for 1D and 2D FFT.
Data formats
- IEEE-754 Floating Point (32-bit float)
- 24-bit mantissa, 8-bit exponent, 2's complement
- 14-bit mantissa, 8-bit exponent, 2's complement
- Specific data format upon request.
Benchmark
FFT/IFFT length |
Texas Instruments C6713 |
Single 4DSP FFT core |
Quad 4DSP FFT core |
256 |
12.3µs |
3.68µs |
920ns |
512 |
27.3µs |
6.24µs |
1.56µs |
1024 |
60.2µs |
11.4µs |
2.85µs |
2k |
132µs |
61.4µs |
15.32µs |
4k |
287µs |
123µs |
30.75µs |
16k |
621µs |
246µs |
61.5µs |
32k |
1.34ms |
492µs |
123µs |
64k |
2.87ms |
1.31ms |
328µs |
128k |
6.12ms |
2.62ms |
655µs |
256k |
13.4ms |
5.24ms |
1.31ms |
512k |
58.1ms |
10.5ms |
2.63ms |
1M |
122ms |
21ms |
5.25ms |
Table 2: 1D FFT benchmark
Radix-32 vs Radix-2
This core is designed around a radix-32 butterfly architecture. With equal performances, the memory resources and bandwidth required by our core are five times less than a design comprising five radix-2 cores in parallel (a floating point radix-2 implementation is currently the only alternative available on the market). At the system level, this means that a single-width PMC module used to perform long transforms with our core achieves the same level of processing performances as a radix-2 implementation spread over two 6U CompactPCI boards bundled with multiple FPGA devices and memories.
Smart IP solutions increase board efficiency and reduce the price of Digital Signal Processing systems!
Target devices
- Xilinx Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3
- Altera Stratix, Stratix II, Cyclone II, Cyclone III
Device resources usage for IEEE-754 implementation
Device |
Slices |
Multipliers 18x18 or DSP48(E) |
Block RAMs |
Fmax (MHz) |
Virtex-5 XC5VLX50T -3 |
6220 |
40 |
36 |
240.7 |
Virtex-4 XC4VLX40 -12 |
12394 |
40 |
36 |
200.2 |
Virtex-II Pro XC2VP40 -7 |
12293 |
40 |
36 |
175.0 |
Spartan-3 XC3S4000-5 |
12835 |
40 |
36 |
105.3 |
Table 1: Device resources usage
Please note that Virtex-4 and Virtex-5 slices are different. Please refer to the Xilinx documentation for more information.
The following graph displays the Signal to Noise Ratio of a Fast Fourier Transform performed over a 1024 points random vector with a 24-bit wide mantissa and 8-bit wide exponent. The software Discrete Fourier Transform was calculated using the FFTw functions.
A fully functional VHDL testbench and bit-true Software development kit are delivered along the FFT/IFFT core for simulation purposes and specific performance characterization.
Up to four FFT cores in parallel can be implemented on the FM482 PMC/PMC-X.
Purchase this core or request more information by sending an email to sales@4dsp.com.
Downloads
Docs
FFT_core_user_manual
(1.1Mb)
FFT_development_kit_user_manual (1.1Mb)
4FFT_PMC/XMC_module(288kb)
Software
Linux_FFT_model (requires_mono)
Windows_FFT_model (requires_.NET)
Testimonial
"4DSP_has_achieved_a_wonderful synergy_with_their_floating_point FFT_core_operating_on_the_FM480. The_quality_of_the_products_and their_integration_has_been_very impressive."
Dan_Abrams CTO,_Luminescent_Technologies
