sFPDP Core
Description
4DSP's serial front panel data port core for FPGA is based on the ANSI/VITA 17.1-2003 standard. This intellectual property core can be implemented on any Xilinx FPGA families. Stellar IP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation.
4DSP has produced a full implementation of the sFPDP IP Core in the FM481 Serial Communication Boards. Please go to the FM481 page to see this turn-key implementation of the 4DSP sFPDP IP Core.
Specifications
- Up to 6Gbps (using MGTs)
- Up to 600MBytes/s per optical transceiver
- Unidirectional and bi-directional links
- Framing supported: dataflow control, PIO per specification, copy mode, copy-loop mode and CRC
- Fully compliant ANSI/VITA 17.1-2003 SFPDP standard
