Documentation
sFPDP Core
Description
4DSP's Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2003 standard. The 4DSP sFPDP IP core is a serial communication protocol that is designed to provide low latency and high transfer rates. Real-time applications benefit from the high performance and low overhead built into the core. This intellectual property core can be implemented on any Xilinx FPGA family and is rated for transfer speeds of up to 5Gbps data rates. The use of fiber optic cables allows sFPDP to operate over long distances (up to 10KM).
The heart of the sFPFP core lies within the sFPDP transceiver module which takes care of encoding and decoding the sFPDP packets. The sFPDP protocol allows connectivity directly to the transmit input and output of a Xilinx MGT or GTP.
This protocol is available pre-ported to a number of PMC - XMC board as a Turn-Key solution, plug-n-play on any PMC - XMC host motherboard. Stellar IP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation.
Specifications
- Up to 5Gbps (using MGTs)
- Up to 230MBytes/s per optical transceiver for 2.5 Gbps, 460MBytes/s for 5Gbps
- Unidirectional and bi-directional links
- Framing supported: dataflow control, PIO per specification, copy mode, copy-loop mode and CRC
- Fully compliant ANSI/VITA 17.1-2003 SFPDP standard
Target Devices
- Xilinx Virtex-4, Virtex-5, Virtex-6, Virtex-7 (Contact factory for Virtex-7, Kintex-7, and Artix-7 availability)