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AS9100C certified


FMC - FPGA Mezzanine Card

C6455 Fixed-Point DSP FMC
FMC-HPC Signal Processor
FMC VITA 57.1 Compliant



The FMC645 is a Digital Signal Processor FMC daughter card based on the Texas Instruments TMS320C6455 device. The FMC645 daughter card is mechanically and electrically compliant with the FMC standard (ANSI/VITA 57.1), has a high-pin count connector and can be used in a conduction cooled environment. This FMC is equipped with power supply and temperature monitoring and offers several power-down modes to switch off unused functions and peripheral interfaces. Several Gigabit differential pairs from the FMC connector are used to implement a PCIe and Serial Rapid IO interface between the FMC and the carrier. Many other digital I/O interfaces are also made available to the FMC carrier. Because of the use of level translators between the DSP and the FMC connector the FMC645 can fully operate on any VITA 57.1 compliant carrier. A 512MB DDR2 SDRAM on-board bank directly connects to the DSP thus providing the FMC645 with the memory resources required for demanding signal processing applications.


  • 1.2GHz TMS320C6455 DSP
  • Fully conduction cooled compliant
  • VITA 57.1-2010 compliant
  • 1.5V to 3.3V VADJ operation
  • Onboard 512MB DDR2 memory
  • 16-pins debug/emulator header option (press-fit)
  • GPIO header option (press-fit)
  • HPC (High-Pin Count) 400-pin connector
  • MIL-I-46058c compliant (optional)

FMC645 Block Diagram



  • Software defined radio legacy DSP applications
  • Video
  • Telecom infrastructure
  • Imaging/medical
  • Wireless infrastructure (WI)

TMS320C6455 Block Diagram Enlarge


The TMS320C64x+™ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. Based on 90-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle. The TCI6482 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

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