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FMC151

FMC - FPGA Mezzanine Card

Dual 14-bit 250Msps A/D
Dual 16-bit 800Msps D/A
FMC VITA 57.1 Compliant

FMC151

  • Description

      The FMC151 is a dual channel ADC and dual channel DAC FMC daughter card. The card provides two 14-bit A/D channels and two 16-bit D/A channels which can be clocked by an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. In addition there is one trigger input for customized sampling control. The FMC151 daughter card is mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1).


      The FMC151 has a low-pin count connector, front panel I/O, and can be used in a conduction cooled environment. The design is based on TI's ADS62P49 dual channel 14-bit 250Msps ADC and TI's DAC3283 dual channel 16-bit 800Msps D/A. The analog signal inputs are DC coupled connecting to MMCX/SSMC coax connectors on the front panel and the input. The input and output have digitally controlled offset correction.


      The FMC151 allows flexible control on clock source, analog input gain, and offset correction through serial communication busses. Furthermore the card is equipped with power supply and temperature monitoring and offers several power-down modes to switch off unused functions, reducing system level power and heat and is well suited for software defined radio (SDR), battery or other low power source applications. This is ideal for applications such as airborne where power demand effects mission range and on-station mission time.

  • Features
      Quad Channel Operation
      2-channels 14-bit A/D up to 250 Msps
      2-channels 16-bit D/A up to 800 Msps
      VITA 57.1-2010 compliant
      Conduction Cooled – Standard Option
      Single ended DC-coupled analog signals.
      Digitally controlled offset correction
      6 MMCX/SSMC connectors available from the front panel
      Clock Source, Sampling Frequency, and Calibration through a SPI communication busses
      Flexible clock tree enables:
      internal clock source (see ordering information for available frequencies)
      external reference clock
      external sampling clock
      Power-down modes to switch off unused functions for system power savings
      Mil-I-46058c Conformal Coating Compliant (optional)
      LPC – Low Pin Count Connector
      LVDS IO signaling

      (Click Block Diagram to Enlarge)

      FMC150 Block Diagram

  • Board Support Package
      Stellar IP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation
      Data analyzer makes it possible to display digitized data real time
      Reference designs that work out of the box are available for multiple platforms, please see tables below
      Can be used on any VITA 57.1 compliant carrier card
      User Manual
      For support, please visit our support forum
      Download the BSP datasheet for more information
  • Application
      Direct RF Down Conversion.
      Software defined radio (SDR).
      RADAR/SONAR.
      Ultra Wideband Satellite Digital Receiver.
      Medical equipment.
      Aerospace and test instrumentation.
  • Environmental
      ENVIRONMENTALLEVEL ALEVEL B
      Operating Temperature0°C to 70°C-40°C to 85°C
      Storage Temperature-50°C to 125°C-50°C to 125°C
      Humidity-Operating0 to 100%
      non condensing
      0 to 100%
      non condensing
      Storage Humidity0 to 100%0 to 100%
      Vibration Random0.1 g2 /Hz
      10 – 3kHz
      0.1 g2 /Hz
      10 – 3kHz
      Shock30g peak30g peak
      CoatingNoneConformal

Talk to us about your algorithmic requirements, 4DSP is a full-service firmware and software development house. We are specialist at high performance FFT and Video Processing. Check with us, we may have IP Cores that meet requirements for your application, right off the shelf.


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