FMC116

FMC - FPGA Mezzanine Card

16-Channel 125MSPS @ 14-bit
FMC-HPC Analog-to-Digital Converter Board
FMC VITA 57.1 Compliant

FMC116

  • Description

      The FMC116 is a sixteen-channel ADC FMC Daughter Card which is fully compliant with the VITA 57.1-2008 standard. The FMC116 provides sixteen A/D 14-bit 125Msps channels which can be sampled by an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. A trigger input for customized sampling control is also available. The FMC116 has the HPC (high-pin count) connector, front panel I/O, and is conduction cooled capable.


      The design is based on Linear Technology's quad channel 14-bit 125Msps A/D with high speed serial DDR LVDS outputs (2-lanes per channel). The analog signal input is DC coupled with offset correction circuitry, connecting from a connector on the front panel.


      The FMC116 allows flexible control on sampling frequency through serial communication busses. Furthermore the card is equipped with power supply and temperature monitoring and offers several power-down modes to switch off unused functions or protect the card from overheating.


      FMC116 Block Diagram

  • Features
      16 channel 14-bit 125 Msps A/D conversion
      Conduction cooled compatible
      ANSI/VITA 57.1-2010 compliant
      Based on LTC2175-14
      1.5V to 3.3V VADJ operation
      Single ended DC coupled inputs
      Programmable DC offset correction
      Flexible clock tree enables
      External or Internal clock
      External clock output
      External or internal reference
      HPC (high-pin count) compatible
      A breakout cable on the front panel makes all clock and trigger signals available on individual coax cables.
      Optional SSMC/MMCX clock and trigger IO on the back of the FMC (consult factory)
      MIL-I-46058c conformal coating (optional)
      FMC116 connector
      Breakout Cable
      (Enlarge)
  • Board Support Package
      4FM GUI offers multiple functions including the ability to monitor voltage and temperature; perform memory tests; measure the PCIe bandwidth; update FPGA firmware; and access StellarIP
      StellarIP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation
      Data analyzer makes it possible to display digitized data real time
      Reference designs that work out of the box are available for multiple platforms, please see tables below
      User manual
      Performance guide
      Portable to the Virtex, Spartan and Stratix FPGA series
      For support, please visit our support forum
      Download the BSP datasheet for more information
  • Application
      High channel count applications
      Software defined radio (SDR)
      RADAR/SONAR
      Wireless communication receivers
      Medical equipment
      Aerospace and test measurement Instruments
  • Performance
      62.5MHz Bandwidth (DC)
      2Vpp input range (1Vpp build option)
      (LV)TTL compatible trigger input, LVTTL trigger output
      0dBm clock input (typ.)
      ±1.25V Offset correction (40µV steps)
  • Environmental
      EnvironmentalAir-cooledConduction-cooled
      ANSI/VITA 47EAC4EAC6ECC1ECC4
      Operating Temperature0C to +55C-40C to +70C0C to +55C-40C to +85C
      Storage Temperature-40C to +85C-50C to +100C-40C to +85C-55C to +105C
      Humidity95%95%95%95%
      Operating Vibration5Hz to 100Hz, PSD = 0.04g2/Hz

      100Hz to 1000Hz PSD = 0.04 gs^2/Hz

      1000Hz to 2000Hz PSD decreasing at 6 dB/ octave
      5Hz to 100Hz, PSD = 0.04g2/Hz

      100Hz to 1000Hz PSD = 0.04 gs^2/Hz

      1000Hz to 2000Hz PSD decreasing at 6 dB/ octave
      5Hz to 100Hz PSD increasing at 3 dB/ octave

      100Hz to 1000Hz PSD = 0.1 g^2/Hz

      1000Hz to 2000Hz PSD decreasing at 6 dB/octave
      5Hz to 100Hz PSD increasing at 3 dB/ octave

      100Hz to 1000Hz PSD = 0.1 g^2/Hz

      1000Hz to 2000Hz PSD decreasing at 6 dB/octave
      Operating Shock20g, 11 millisecond, half-sine or 20g, 11 millisecond, terminal sawtooth shock pulses in all three axes20g, 11 millisecond, half-sine or 20g, 11 millisecond, terminal sawtooth shock pulses in all three axes40g, 11 millisecond shock half-sine or 40g, 11 millisecond, terminal sawtooth shock pulses in all three axes40g, 11 millisecond shock half-sine or 40g, 11 millisecond, terminal sawtooth shock pulses in all three axes
      Operating Altitude-1500 ft to 60,000 ft
      (with airflow)
      -1500 ft to 60,000 ft
      (with airflow)
      -1500 ft to 60,000 ft-1500 ft to 60,000 ft
      Conformal CoatingOptionalOptionalOptionalOptional

Talk to us about your algorithmic requirements, 4DSP is a full-service firmware and software development house. We are specialists at high performance FFT and Video Processing. Check with us, we may have IP Cores that meet requirements for your application, right off the shelf.